LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY memory IS
  port(
    fpga_clk      : in std_logic;
    fpga_reset_n  : in std_logic;
    
    rw_fft        : in std_logic;
    
    address_eq    : in integer range 0 to 255;
    address_fft   : in integer range 0 to 255;
    address_cont  : in integer range 0 to 255;
    
    enable_fft    : in std_logic;
    enable_eq     : in std_logic;
    enable_cont   : in std_logic;
    
    data_in_re_fft : in integer range -8388608 to 8388607; -- for time domain this is the only one that matter
    data_in_im_fft : in integer range -8388608 to 8388607;
    data_in_re_eq : in integer range -8388608 to 8388607; -- for time domain this is the only one that matter
    data_in_im_eq : in integer range -8388608 to 8388607;
    data_in_re_cont : in integer range -8388608 to 8388607;
    
    
    data_out_re   : out integer range -8388608 to 8388607; -- for time domain this is the only one that matter
    data_out_im   : out integer range -8388608 to 8388607
  );
END ENTITY memory;

ARCHITECTURE arch OF memory IS
  type memory is array(255 downto 0) of integer range -8388608 to 8388607;
  signal mem_re : memory;
  signal mem_im : memory;
BEGIN
process(fpga_clk)
begin
  if rising_edge(fpga_clk) then
    if fpga_reset_n = '0' then
       
    elsif enable_fft = '1' then
      if rw_fft = '1' then
        mem_re(address_fft) <= data_in_re_fft;
        mem_im(address_fft) <= data_in_im_fft;
      else
        data_out_re <= mem_re(address_fft);
        data_out_im <= mem_im(address_fft);
      end if;
      
    elsif enable_eq = '1' then
        data_out_re <= mem_re(address_eq);
        data_out_im <= mem_im(address_eq);  
        mem_re(address_eq) <= data_in_re_eq;
        mem_im(address_eq) <= data_in_im_eq;
        
    elsif enable_cont = '1' then
      data_out_re <= mem_re(address_cont);
      mem_re(address_cont) <= data_in_re_cont;
      
 
    end if;
  end if;
end process;

END ARCHITECTURE arch;

